ram ddr4 A few diagrams allow you to easily understand the crosstalk of DDR
harddriveSSD OEMram DDR4 microsignal | lets you evaluate crosstalk of high-speed serial signalsram ddr4, you would say their crosstalk is below -40db ram DDR4, no effect. But if you were asked to evaluate the crosstalk of a parallel signal like DDR, you say crosstalk of DQ0 and DQ1 -30db, crosstalk of DQ1 and DQ2 -25db, crosstalk of DQ2 and DQ3… You count slowly, I’ll go first.
According to past experience, today everyone will come to work in the company with an extremely heavy heart, Mr. Gao Gao also expressed a deep understanding of Ha, so today’s article is very concise and imagery, in order to meet everyone’s desire not to use more brains today. Remember that the topic of artificial intelligence was mentioned in the previous articles, so we will continue to talk about a little technical stuff. In the rapid upsurge of artificial intelligence, DDR modules as the core computing power have undoubtedly made a big splash. Because in the pursuit of ultra-large computing power, people have higher and higher requirements for DDR capacity and speed. The computing power card that our Mr. High-Speed contacts is smaller than the other, but there is more and more trend of DDR modules on the board, with 4 channels, 8 channels, or even more at every turn. And while the number of particles continues to increase, the speed we require is basically getting higher and higher, basically starting from 2400Mbps, and the highest has done 3200Mbps. Coupled with the fact that the density of the board is getting smaller and smaller, from the design of various DDRs that we have been exposed to for more than a year, it is no no exaggeration to say that the design difficulty of DDR may have exceeded the imagination of many people….
Peers who have done DDR design know that under the very dense particle arrangement, if you want to successfully pull out all the signals, you may have to die, and then after the conduction, you have to grasp your hand firmly to shake it to make you want to chop the equal length of your hand (5mil, 2mil, we have seen customers ask to do 1mil… When you think you can finish the work, the customer also has to look like discussing with you and say if you can open the distance a little more.
line… Our design engineers are very rigorous, and it is also love to be able to pull 1mil, although they may not know what the use of the hard pulled 1mil is, just like what is the use of the hard work of 2mil isometric when doing equal length.
The general result is this: after our engineers continue to struggle, time has almost passed, and the customer has finally understood the pain of our engineers, and everyone finally forcibly reached a consensus: hard work, or it will be good. Finally, there is no need to do stricter isometric lengths, and finally there is no need to open the 0.5mil spacing. Although the customer’s heart is thinking: in fact, it should be able to continue….
When the length is done, the spacing seems to be no longer widened, and it is handed over to our SI members for simulation, and in our eyes, the results of such a set of data signals are already very good. It goes something like this:
From the Aperture of this set of data signal eye diagrams, the margin of the entire high and low levels is very large, and such an eye diagram must be PASS in actual debugging. But if I mark some points for everyone to look at the same eye diagram again, you may be a little surprised: why my equal length has reached 2mil, and the spacing has been stretched to the point that it can no longer be opened, but look at the delay of this set of data is actually 50ps worse (blue mask below), and the amplitude oscillation above the level is also more than 100mV (red mask below).
The data signal is strictly point-to-point, our impedance is 40 ohms, and then our chip driver and chip receive ODT are also 40 ohms, which shows that such delays and level oscillations are not caused by impedance mismatched reflections (at least not a large part). That’s when we focused on crosstalk, which is difficult to analyze.
from our professional point of view, it is indeed crosstalk to carry this pot. Here we will not talk about some very complex theories and formulas, we will only use the following figures to let you understand how crosstalk affects our level oscillation and delay.
two adjacent lines will have three transmission modes, which are as follows:
Then after the attack signal reaches the receiving end, their result is like this:
here are two questions you might want to ask :
1, why is the time to reach different? The common mode speed is slow, the differential mode speed is fast, and the static row is in the middle. Because under the influence of common mode, the capacitivity between the two lines is the weakest; Under the influence of differential mode, the two lines have the strongest capacitivity, and at this time, just like the differential line, the two lines refer to each other, so the transmission delay is the fastest.
2, why is the level amplitude different? Similarly, in common mode, the two line levels are in the same direction, complement each other, and the amplitude is high; In differential mode, the levels of the two wires are reversed, canceling each other out, and the amplitude is reduced.
so when these two lines run different random patterns, it’s not surprising that one of the lines you see is signaled like this.
and then back to our set of DDR data signals above, it is more complicated for them, a set of 8 DQ plus DM signals have different patterns, and the crosstalk between them causes their eye diagrams to show different delays and level oscillations. In fact, the theory may be complicated, but this is how it manifests. In short, it is more intuitive and convincing to analyze the crosstalk of parallel signals such as DDR from a time-domain perspective. Of course, the difficulty is also here, you must analyze the entire set of signals or even the signals of the entire channel together to maximize the impact of crosstalk.
so we made 5mil or even smaller equal length compared to the 50ps of the simulated waveform above, which is really insignificant. In fact, crosstalk does have a more serious impact in the DDR module, just imagine, we feel that the 5mV crosstalk in the high-speed serial signal is very large, and there can be hundreds of mV in the DDR module. Of course, there is still a big difference between the two, the eye diagram margin of the high-speed serial signal is still much smaller than DDR, generally only within 100mV, our current DDR system has a high and low level margin of several hundred mV, and the rate of DDR also determines that the loss of the trace basically has little impact on it.
so our crosstalk results of 100mV are acceptable, and the margin is still large from the overall waveform. But as the DDR level gets lower and lower, the corresponding headroom will definitely become smaller and smaller, and by that time the crosstalk may be very serious.
Question: How do you reduce crosstalk between DDR signals in your design? harddriveSSD OEMram ddr4