disco ssd What is the difference between DDR and DDR2 What is he difference between DDR3 and DDR2 [Introduction]
solid state drive SSD OEMdisco SSD
DDR2 and DDR, respectively
1. Rate and prefetch
DDR2 actually operates at twice the frequency of DDRdisco.” SSD, DDR2 memory has twice the 4-bit expected capability of standard DDR memory.
2. Package and voltage
DDR package is TSOPIIdisco ssd, DDR2 package is FBGA;
The standard voltage for DDR is 2.5V and the standard voltage for DDR2 is 1.8V.
3, bit pre-fetch
DDR is 2bit pre-fetch and DDR2 is 4-bit pre-fetch.
4. Introduction of new technology
DDR2 introduces OCD, ODT and POST
(1) ODT: ODT is the termination resistor of the built-in core, its function is to make the DQS, RDQS, DQ and DM signals consume at the termination resistance. prevent these signals from forming reflections on the circuit;
(2) Post CAS: It is set to improve the efficiency of DDR2 memory;
In the absence of the pre-CAS function, the addressing operation of other L-banks may be delayed due to the current line of CAS commands occupying the address line and make the data I/O bus idle, when the pre-CAS is used, the command conflict is eliminated and the interest rate of the data I/O bus is increased.
(3) OCD (Off-Chip Driver): Offline drive adjustment, DDR2 can improve the integrity of the signal through OCD
The main purpose of OCD is to adjust the voltage at the I/O interface to compensate for the pull-up and pull-down resistor values, in order to minimize the deviation between the DQS and DQ data signals. During the tuning, the DQS high level and DQ high level are tested separately for synchronization with DQS low level and DQ high level, and if the requirements are not met, the pull-up/pull-down resistance level is transmitted by setting the address line of the burst length, and the OCD operation is not exited until the test is passed.
DDR3 and DDR2 respectively
1. DDR2 is 1.8V, DDR3 is 1.5V;
2. DDR3 adopts CSP and FBGA packages, 8-bit chips use 78-ball FBGA packages, 16-bit chips use 96-ball FBGA packages, and DDR2 has three specifications: 60/68/84-ball FBGA packages;
3, the number of logical banks, DDR2 has 4 Bank and 8 Bank, and DDR3 has 8 starting banks;
4, burst length, because DDR3 is expected to be 8bit, so the burst transmission period (BL, Burst Length) is also fixed bit 8, and for DDR2 and early DDR architecture systems, BL=4 is also commonly used, DDR3 adds a 4-bitBurst Chop (burst mutation) mode for this, that is, a BL=4 read operation plus a BL= 4 write operation to synthesize a BL=8 data burst transmission, then this burst mode can be controlled through the A112-bit address line;
5, addressing timing (Timing), DDR2 AL is 0~4, DDR3 is 0, CL-1 and CL-2, in addition, DDR3 also adds a timing parameter – write delay (CWD);
6, bit pre-fetch: DDR2 is 4bit pre-fetch, DDR3 is 8-bit pre-fetch;
7, new function, ZQ is a new pin, on this pin is connected with a 240 ohm low tolerance reference resistor, new exposed SRT (Self-Reflash Temperature) programmable temperature control memory clock frequency function, new PASR (PartialArray Self-Refresh) local bank refresh function, It can be said that more efficient data reading and writing for the entire memory bank to achieve power saving effect;
8. The reference voltage of DDR3 is divided into two, namely VREFCA for command and address signal services and VREFDQ for data bus services, which will effectively reduce the signal-to-noise level of the system data bus;
9) point-to-point (p2p), which is an important change made to improve system performance.